The present invention relates generally to phase comparison methods and/or circuits, and phase locked loop (PLL) type circuits, and more particularly to a phase comparison method and/or circuit, and phase locked loop (PLL) type circuit that can control the capacitance of varactors, or the like, in a voltage controlled oscillator (VCO).
A phase locked loop (PLL) circuit typically includes a phase comparison circuit that can receive an input signal and feedback signal by way of a feedback loop. The feedback serves to adjust a frequency of the feedback signal to match that of the input signal. PLL circuits enjoy a wide variety of applications in various fields.
A PLL circuit can be considered xe2x80x9clockedxe2x80x9d when the phase comparison circuit indicates essentially no phase difference between the input signal and feedback signal, and/or when the phases of the input signal and feedback signal match one another, and maintain such a phase match.
A phase difference between an input signal and a feedback signal is detected by a phase comparison circuit. Such a phase difference can be translated into a voltage and applied to a variable capacitance element (a varactor), which may form part of resonator within a voltage controlled oscillator (VCO) in a later stage of the PLL circuit. A varactor provides a capacitance that varies in accordance with an applied voltage. Thus, in the above PLL arrangement, a varactor capacitance can reflect the phase difference between the input signal and the feedback signal.
A conventional technique that includes a phase comparison circuit for controlling a varactor is disclosed in U.S. Pat. No. 6,150,891 (hereinafter the ""891 patent). The ""891 patent shows a technique in which a plurality of signals are generated with a shift register, and such signals are applied to corresponding phase comparison circuits. FIG. 8 shows a conventional PLL circuit like that described in the ""891 patent. In FIG. 8, a conventional PLL circuit includes a shift register circuit 200, a phase comparison circuit 201, a voltage controlled oscillator (VCO) 202, a frequency divider 203 having a frequency division ratio of N (an N-frequency divider), a frequency divider 204 having a frequency division ratio of Q (a Q-frequency divider), and a frequency divider 205 having a frequency division ratio of R (an R-frequency divider).
In the conventional arrangement of FIG. 8, a shift register 200 receives a signal SET as an input that is generated by frequency dividing an output signal fout by xe2x80x9cNxe2x80x9d within N-frequency divider 203. Shift register 200 may also receive a signal CLKQ at a clock input that is generated by frequency dividing an output signal fOUT by xe2x80x9cQxe2x80x9d within Q-frequency divider 204. Shift register 200 may then output a number of predetermined signal SIGi (where i=0 to M) that are provided to phase comparison circuit 201.
Phase comparison circuit 201 includes M+1 phase difference detection circuits 210. Each of the phase detection circuits 210 receives as inputs, one of the signals SIGi and a reference signal REF. A reference signal REF is generated by frequency dividing an input reference signal fREF by xe2x80x9cRxe2x80x9d within R-frequency divider 205. Each phase detection circuit 210 can output a voltage signal to the VCO 202 that corresponds to a detected phase difference between their respective input signal SIGi and reference signal REF. A VCO 202 can change capacitance values of varactors of a resonator according to voltage signals received from phase detection circuits 210. Such changes in varactor capacitance values can control the oscillation frequency of output signal fOUT. The PLL circuit of FIG. 8 can be considered locked when the frequency of output signal fOUT matches that of reference signal fREF.
FIG. 9 sets forth a timing chart that illustrates the operation of a phase comparison circuit 201. FIG. 10 is a diagram illustrating the configuration of a phase difference detection circuit 210. The operation of a phase comparison circuit 201 will now be described with reference to FIGS. 8, 9 and 10. As noted above, a conventional phase comparison circuit 201 can include xe2x80x9c0xe2x88x92Mxe2x80x9d phase difference detection circuit 210. Thus, if M=2, a phase comparison circuit 201 includes three phase difference signals that receive signals SIGi as inputs (where i=0 to M), respectively.
Referring to FIG. 10, conventional phase difference detection circuit 210 can receive a signal SIG0 as an input. A conventional phase difference detection circuit 210 includes a voltage source Vnom for generating a predetermined initial potential, a logical sum circuit AND0, capacitors C0a and C0b, a resistor R0, and three switches SW0a, SW0b, and SW0c. It is understood that switches SW0a, SW0b and SW0c are operated to not close at the same time. In addition, an output node N0 can be connected to a capacitor C0a, and provide an output voltage to a VCO. Each of the 0-M phase difference detection circuits 210 receiving a signal SIGi can have the same general configuration as that of FIG. 10, except for the particular input signal received.
A shift register 200 receives as inputs the signals CLKQ and SET. The signal CLKQ is obtained by frequency-dividing output signal fout by Q and the signal SET is obtained by frequency dividing output signal fout by N. According to such input signals, shift register 200 generates signals SIGi as outputs. Frequency division ratios N and Q of frequency dividers 203 and 204, respectively, are set to meet the relationship N greater than Q. Thus, the cycle of signal CLKQ can be shorter than that of signal SET. Further, signals SIGi generated by shift register 200 rise concurrently with the rise of signal SET and fall later than the fall of signal SET by i cycles of the signal CLKQ, respectively. Thus, signals SIGi have the timing as set forth in FIG. 9.
While a signal SET is at a high level, a phase difference detector 210 supplies the potential of capacitor C0b to capacitor C0a by way of switch SW0a. Such a potential can represent a phase detection result for a previous cycle. In this way, a potential corresponding to a phase detection operation can be presented at node N0.
Switch SW0b may then close to charge capacitor C0b with an initial potential Vnom. In this way an initial potential can be established on capacitor C0b. 
Upon the fall of a signal SET, an AND gate AND0 may close according to the logical combination of the signal REF and SIG0. That is, switch SW0c will close in the time period that signals REF and SIG0 are both high. If switch SW0c is closed, electric charge from capacitor C0b will discharge to ground through resistor R0. Thus, the initial potential of capacitor C0b can be discharged for a time period corresponding to a phase difference between the signal REF and SIG0. In this way, a potential corresponding to a phase difference can be established on capacitor C0b. 
In the particular example of FIG. 9, the signal SIG0 falls before the rise of signal REF. Thus, there is no period time after the signal SET falls during which signals REF and SIG0 are both high. Consequently, switch SW0c remains open, and essentially no charge on capacitor C0b is discharged through resistor R0.
From the above description it is understood that each phase difference detection circuit 210 closes a switch SWic (where i=0xe2x88x92M) for a period of time corresponding to a phase difference between one of the signals SIGi and REF. In particular, each phase difference detection circuit can detect the time between the rise of signal REF and the fall of signal SIGi, and discharge a capacitor Cib during such a time period. As noted previously, the potential established across capacitor Cib is supplied to corresponding capacitor Cia when signal SET rises once again to a high level.
FIG. 11 shows changes in voltage due to a discharge of capacitors Cib that corresponds to the timing of FIG. 9. Potentials at output nodes Ni of phase comparison circuit 210 are indicated by black circles in FIG. 11. As shown, output node N0, corresponding to the case where signal SIG0 falls before the rise of signal REF, can have the potential Vnom, as capacitor C0b is not discharged because switch SW0c is not turned on. The potential at node N1 is lower than that of N0 by an amount corresponding to the difference between the point at which signal REF rises and signal SIG1 falls. The potential appearing on subsequent nodes have time difference values shifted by one clock cycle (xcex94t) of signal CLKQ.
Output voltages of the phase difference detection circuits 210 can control varactors connected in parallel within VCO 202. If the capacitance of such varactors is given by Ci, then a total capacitance xcexa3C (composite capacitance) of the parallel-connected varactors can be as follows:
xcexa3C=C0+C1+. . . +CM. 
The VCO 202 can oscillate at a resonance frequency determined by the composite capacitance xcexa3C. In this way, an output frequency fOUT can be altered in response to a phase difference between signal SET and signal REF. When the frequency of signal REF essentially equals that of the signal SET, the PLL circuit can be considered locked.
Conventionally, a capacitance presented by a varactor can have a non-linear relationship to an applied control voltage. This can lead to drawbacks in PLL operation. In particular, if a range of phase adjustment within a PLL is large, characteristics of the oscillation frequency of VCO 202 can be deteriorated. In the above-described conventional PLL circuit, capacitance values of individual varactors are controlled by corresponding phase difference detection circuits 210. As a result, the characteristics of a resulting composite capacitance xcexa3C versus a phase difference can be more linear as the number varactors provided within VCO 202 is increased. Thus, frequency characteristics of a VCO 202 can be enhanced by increasing the number of varactors.
However, in the above-mentioned conventional PLL circuit, individual varactors are controlled in a parallel number by a corresponding signals SIGi generated by a shift register 200. Thus, if a frequency characteristic is to be improved by increasing the number of varactors, a shift register 200 has to be increased in scale to generate such additional signals. This can undesirably increase circuit size and current consumption for the PLL circuit.
In addition, in the conventional approach signals SIGi have edges that are shifted within shift register 200 according to clock signal CLKQ. However, such signals SIGi all need to fall prior to a subsequent rise in signal SET. Thus, an increase in the number of signals SIGi can require a shorter cycle for clock signal CLKQ. When the clock signal CLKQ is generated by frequency dividing the output signal of VCO 202, a frequency divider (e.g., Q frequency divider 204) can be required to have a small frequency division ratio. This can also increase circuit scale and power consumption.
Thus, as is understood from above, as the number of varactors is increased, it is possible to enhance the frequency characteristics of the VCO 202 with respect to a detected phase difference. However, in a conventional approach, increasing the number of varactors requires an increase in the number of corresponding phase difference detection circuits 210. Increasing the number of phase difference detection circuits 210 requires reconfiguring the shift register 200 to increase the number of output signals SIGi that are generated.
In light of the above, it would desirable to provide a phase comparison method, phase comparison circuit, and/or PLL circuit having a number of varactors that are individually controlled, but not suffer from increased circuit scale and power consumption presented by conventional approaches. It would also be desirable to provide such a phase comparison method, phase comparison circuit, and/or PLL circuit, in which the number of varactors may be readily increased without the drawbacks of conventional approaches.
The present invention may include a method of generating phase comparison signals depending on the phase relationship between a first signal and a second signal. The method may include: (a) generating a first voltage signal of a predetermined sequence that has a value that depends on a time elapsed from the activation of the first signal, and activating a first trigger signal of the sequence if the first voltage signal exceeds a threshold limit; (b) generating at least one subsequent voltage signal of the sequence that has a value which depends on a time elapsed from the activation of a previous trigger signal of the sequence; and (c) activating at least one subsequent trigger signal of the sequence if the at least one subsequent voltage signal exceeds a threshold limit. The method may further include outputting the first voltage signal and the at least one subsequent voltage signal as phase comparison signals in response to the second signal.
According to one aspect of the embodiments, a step (a) can include activating a first of a plurality of voltage signal generating circuits in the sequence, a step (b) can include activating a subsequent voltage signal generating circuits of the sequence, and a step (c) can include deactivating all of the voltage signal generating circuits.
According to another aspect of the embodiments, the method may further include a step (d) providing the first and at least subsequent voltage signals to corresponding varactors that each generate a corresponding capacitance, the corresponding capacitances being arranged in parallel.
According to another aspect of the embodiments, the method may further include a step (e) generating an oscillating signal with a voltage controlled oscillator that includes the parallel connected capacitances, a frequency of the oscillating signal corresponding to the variable capacitance of the parallel connected capacitances.
According to another aspect of the embodiments, a step (a) can include discharging a first capacitor to generate the first voltage signal, and activating the first trigger signal if the first voltage signal falls below the threshold limit. In addition, a step (b) can include discharging a subsequent capacitor to generate the subsequent voltage signal, and activating the subsequent trigger signal if the subsequent voltage signal falls below the threshold limit.
According to another aspect of the embodiments, a step (a) can include charging a first capacitor to generate the first voltage signal, and activating the first trigger signal if the first voltage signal rises above the threshold limit. In addition, a step (b) can include charging a subsequent capacitor to generate the subsequent voltage signal, and activating the subsequent trigger signal if the subsequent voltage signal rises above the threshold limit.
According to another aspect of the embodiments, a step (c) can include transferring the first voltage signal from a first dischargeable capacitor to a first output capacitor, and transferring the subsequent voltage signal from a subsequent dischargeable capacitor to a subsequent output capacitor.
According to another aspect of the embodiments, the predetermined sequence can be greater than two. Step (b) can generate a second subsequent voltage signal of the sequence. In addition, step (b) can be repeated to generate a third subsequent voltage signal of the sequence.
The present invention may also include a phase comparison circuit for generating phase comparison signals according to a phase relationship between a first signal and a second signal. The phase comparison circuit can include a plurality of voltage signal generation circuits that are each activated in response to corresponding activation signals to generate a voltage signal with a value that depends on a time elapsed from the activation of the corresponding activation signal, and to activate a trigger signal if the voltage signal exceeds a predetermined limit. The voltage signal generating circuits can have a sequence with a subsequent voltage signal generating circuit being activated in response to the trigger signal of the previous voltage signal generating circuit of the sequence, and the first voltage signal generating circuit of the sequence being activated in response to the first signal. In addition, the voltage signal generating circuits can be deactivated in response to the second signal, and the voltage signals of the voltage signal generating circuits can be output as phase comparison signals.
Such an arrangement can dispense with the need to generate different timing signals for multiple voltage signal generation circuits, as the embodiments can include sequential activation of such circuits. Thus, it can be possible to reduce circuit size and power consumption over conventional approaches. In addition or alternatively, it can be possible to increase the number of voltage signal generation circuits without having to increase the size of a signal generation circuit, such as a shift register, as is done in conventional approaches.
According to one aspect of the embodiments, each voltage signal generating circuit can include a capacitor having a potential that is set to a predetermined value prior to the activation of the corresponding activation signal. The potential may then be altered in response to the activation of the corresponding activation signal. The potential may also be output as the voltage signal of the voltage signal generating circuit.
According to another aspect of the embodiments, the phase comparison circuit may also include a signal generation circuit that generates a sample signal followed by a charge signal followed by a deactivation signal. In addition, each voltage signal generating circuit can set the capacitor potential to a predetermined value in response to the sample signal. Such a potential can be altered in response to a charge signal and output in response to a deactivation signal.
According to another aspect of the embodiments, a signal generation circuit can receive a clock signal and generate a sample signal xe2x80x9caxe2x80x9d clock cycles after the activation of the first signal, generate a charge signal xe2x80x9cbxe2x80x9d cycles after the activation of the first signal, and generate a deactivation signal xe2x80x9ccxe2x80x9d cycles after the activation of the first signal. Such clock signal values can have the relationship: c greater than b greater than a.
According to another aspect of the embodiments, a phase comparison circuit can also include a plurality of variable capacitance capacitors (varactors) connected in parallel with one another. Such varactors can have capacitance values that vary according to the phase comparison signals. In addition, a voltage controlled oscillator can generate an output signal that oscillates at a frequency which depends upon the parallel connected varactors.
Thus, even in an arrangement where such variable capacitance capacitors are individually controlled, the number of such variable capacitance capacitors can be increased without necessarily increasing circuit size or power consumption. Such a result can be possible as a shift register, or the like, does not have to be modified to generate additional control signals, due to the sequential activation of the voltage signal generating circuits.
According to another aspect of the embodiments, each voltage signal generating circuit can include a sample capacitor coupled to a voltage node by a first switch, a reset capacitor coupled to the voltage node and to a first potential by a second switch, a resistance coupled to the voltage node and to a second potential by a third switch, and a logic circuit having an input coupled to the voltage node and an output that generates the trigger signal.
The present invention may also include a phase locked loop circuit that includes a plurality of phase difference detection circuits. Each phase difference detection circuit can include an enable input, and can generate an output voltage signal and a trigger signal. The output voltage signal can vary according to a time difference between the activation of an enable signal at the enable input and a termination signal. Such a termination signal can be common to the phase difference detection circuits. In addition, a trigger output of one phase difference detection circuit being coupled to the enable input of another phase difference detection circuit.
According to one aspect of the embodiments, a phase locked loop circuit can also include a voltage controlled oscillator (VCO) that varies an output signal frequency according to values received at a plurality of control inputs. In addition, each output voltage signal can be coupled to one of the VCO control inputs.
According to another aspect of the embodiments, such VCO control inputs can provide control voltage values to varactors.
According to another aspect of the embodiments, each phase difference detection circuit can include a first switch that couples a reset capacitor first node to an output capacitor first node, a second switch that couples a first voltage to the reset capacitor first node, and a third switch that enables a current path to the reset capacitor first node.
According to another aspect of the embodiments, a phase locked loop circuit can also include a signal generator circuit that activates a sample pulse followed by a reset pulse followed by an end pulse. In addition, each phase difference detection can include a first switch being activated by the sample pulse, a second switch being activated by the reset pulse, and third switch being activated by a logical combination of the end pulse and the signal received at an enable input.
According to another aspect of the embodiments, a signal generator circuit can activate a sample pulse a first number of clock cycles following the activation of a reference signal, can activate a reset pulse a second number of clock cycles following the activation of a reference signal, and can activate an end pulse a third number of clock cycles following the activation of a reference signal. Such a third number can be greater than the second number and the second number can be greater than the first number.